Dynamic coarse grained reconfigurable architectures

Coarse grained reconfigurable processors have gained more popularity in the last years, as they introduce a new way for a dynamic and programmable execution similar to FPGA and tend to achieve the performance of application specific hardware. The reconfigurability on instruction level grants these architectures a big dynamicity and ability to embrace the diversity of the applications. Nevertheless, managing the hardware resources in the software prevents from undertaking many dynamical reactions needed by the reconfiguration task at runtime to be adaptive to the dynamic program execution. However, an adaptive architecture can face the diversity of applications dynamically in the hardware without any software manipulation. On the other hand, the need for more flexibility to manage the underlying hardware structures increases the demands on the configuration hardware unit. This work focuses on the design and optimization of reconfigurable coarse grained processors. In addition, it concerns with the implementation of the configuration task in the hardware. The Grid Alu Processor (GAP) is presented as baseline architecture for the design and optimization issues. We combine the characteristics of superscalar processors and coarse grained reconfigurable architectures to achieve a dynamicity and performance beyond that of out-of-order superscalar processors. Hence, the GAP comprises an in-order superscalar frontend and reconfigurable backend. A special config-